1. Field of the Invention
The present invention relates to a low offset clamp bias circuit of a memory. More particularly, the present invention relates to a low offset clamp bias circuit applied to a memory which having multilevel memory cells.
2. Description of Related Art
At present, various kinds of memory, such as flash memory, dynamic random access memory (DRAM), and static random access memory (SRAM), the accuracy in reading, writing, or erasing data therein has become one of the major factors for manufacturers to develop memory products, and is the key for improving the competitiveness of a memory product.
It is known that the aforementioned memory has a plurality of memory cell array areas, and each memory cell array area has a plurality of memory cells, which may be multilevel memory cells. FIG. 1 is a diagram of a conventional clamp bias circuit applied to the drain side voltage Vd of a memory cell, wherein the gate of a clamp transistor Mclamp receives a clamp voltage Vclamp and then the source side of the clamp transistor Mclamp provides a voltage Vdr to the memory cell array area 101. Wherein, in the memory cell array area 101, the transistors Mpassgate and Mselect are controlled by a controlling mechanism unit 103 to select the memory cell to be read, written, or erased. For example, when the memory cell 101a is to be read, the voltage Vdr is provided to the drain side of the memory cell 101a so that the memory cell 101a produces a memory cell current Icell.
Generally speaking, resistive loading effect may be produced between the transistors Mpassgate and Mselect, and between the transistor Mselect and the memory cell 101a due to the inherent architecture of the memory, which make the memory cell current Icell produced by the memory cell 101a will reduce the read margin and further the data in the memory cell 101a are read incorrectly. FIG. 2 is a table illustrating the differences of the drain side voltage Vd of the memory cell 101a in FIG. 1 when the memory cell 101a produces different memory cell currents Icell. Referring to both FIG. 1 and FIG. 2, the table as shown in FIG. 2 is mainly for showing the variations of the drain side voltage Vd of the memory cell 101a when the memory cell 101a produces different memory cell currents Icell, for example, 5 uA or 25 uA, and with the aforementioned resistive loading effect in consideration.
It can be understood from the table in FIG. 2 that the clamp voltage Vclamp received by the gate of the clamp transistor Mclamp is 2.833V, and when the memory cell current Icell produced by the memory cell 101a is 5 uA or 25 uA, the voltage Vdr provided by the source side of the clamp transistor Mclamp is respectively 1.709V and 1.607V, thus the variation is 0.102V (102 mV). Next, when the resistive loading effect is considered and the memory cell current Icell produced by the memory cell 101a is 5 uA or 25 uA, the drain side voltage Vd of the memory cell 101a is respectively 1.675V and 1.441V, thus the variation is 0.234V (234 mV). As described above, when the memory cell 101a produces different memory cell current Icell and the resistive loading effect is considered, the drain side voltage Vd of the memory cell 101a changes about 234 mV, thus, the memory cell current Icell produced by the memory cell 101a will reduce the read margin, resulting in a data reading error to the memory cell 101a. 
To improve the accuracy in reading, writing, or erasing memory data, conventionally the drain side voltage Vd supplied to each memory cell is fixed so that the accuracy in no matter reading, writing, or erasing memory data can be improved.
FIG. 3 is a diagram illustrating a conventional clamp bias circuit for reducing the variation of the drain side voltage Vd of a memory cell. Referring to FIG. 3, the voltage Vdr provided by the source side of the transistor Mclamp is clamped to be equal in [(R303+R305)/R305]*Vref by adding an operation amplifier 301 and resistors 303 (R303) and 305 (R305), wherein the Vref is a reference voltage, so as to fix the drain side voltage supplied to each memory cell in the memory cell array area 307 (which is similar to the memory cell array area 101 in FIG. 1, therefore, the details will not be described herein), so that the memory cell current Icell produced by each memory cell in the memory cell array area 307 falls out of the read margin, accordingly, data in each memory cell in the memory cell array area 307 can be read accurately. However, even though the purpose of accurately reading the data in each memory cell in the memory cell array area 307 can be achieved by the clamp bias circuit in FIG. 3, which is used for reducing the drain side voltage variation of a memory cell, the fabricating cost and power consumption of the memory are increased, and the surface area taken by the memory at designing the chip is increased too.